The present invention relates to a method for manufacturing a capacitor for a semiconductor device, and more particularly, to a method for manufacturing a capacitor for a semiconductor device by which capacitance can be easily increased.
The decrease in cell capacitance accompanying reduction in the memory cell area is a serious hindrance to increasing the cell packing density of a dynamic random access memory (DRAM), as it causes a degraded read-out capability and an increase in the soft error rate of a memory cell and consumes excessive power during low voltage operation. Thus, it is necessary to increase cell capacitance commensurately with increases in the cell packing density.
Generally, in a highly integrated DRAM (e.g., 64 Mb) employing a two-dimensionally structured, stacked memory cell, sufficient cell capacitance cannot be obtained even though a high dielectric constant material, e.g., tantalum pentoxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been proposed to increase cell capacitance, e.g., the double-stacked, fin, spread-stacked, and cylindrical electrode structures have all been proposed.
Since both the outer and inner electrode surfaces can be utilized as an effective capacitor area, the cylindrical three-dimensional structure, in particular, has been recognized as the most suitable for an integrated memory cell circuit which is 64 Mb or higher in capacity. However, the simple cylindrical structure cannot provide sufficient cell capacitance for an integrated memory cell device which is 256 Mb or higher in capacity. Therefore, various new structures have been proposed to increase cell capacitance by improving the cylindrical structure.
The CROWN cell structure, suggested by Toru Kaga in 1991, increases the cell capacitance by forming the cylindrical electrode as a crown-shaped electrode having a double-wall structure (see IEEE Transactions on Electron Device `91, "Crown-Shaped Stacked-Capacitor Cell for 1.5 V Operation 64 Mb DRAMs").
However, the CROWN cell has a disadvantage in that it cannot maximize capacitance because i-line (365 nm) exposure technology used in the manufacturing process of conventional 64 Mb DRAMs cannot reduce the distance between neighboring capacitors of about 0.8.times.1.6 .mu.m.sup.2 cell size to 0.2 .mu.m (the limitation imposed by the i-line photolithographic technology) or below.
The present inventors (Ahn et al.) have developed a novel method for manufacturing a capacitor to overcome the above-described disadvantages of the conventional techniques, which novel method is disclosed in Korean patent application No. 93-5901, the disclosure of which is herein incorporated by reference.
FIGS. 1 to 3 are sectional views depicting successive steps of the Ahn et al. method for manufacturing a capacitor.
Referring to FIG. 1, after forming a pair of transistors commonly sharing a drain region 6 and a bit line 11 connected thereto, and each having a source region 4 and a gate electrode 8, on an active region of a semiconductor substrate 1 disposed between adjacent field oxide layers 2, an insulating layer 13 for insulating the transistor is formed on the entire surface of the resultant structure. Subsequently, after forming a planarizing layer 15 for planarizing the surface of the substrate 1 on the resultant structure, silicon nitride and oxide layers are sequentially deposited thereon, thereby forming an etch-blocking layer 17 and a first material layer 29. Next, after forming contact holes by etching the resultant structure over source regions 4, a first conductive layer 50 is formed by depositing an impurity-doped polycrystalline silicon by a chemical vapor deposition (CVD) method. Subsequently, after forming second and third material layers by sequentially depositing oxide and polycrystalline silicon layers on the entire surface of the resultant structure by a CVD process, a first pattern 55 for forming cylindrical electrodes is formed by patterning the third material layer by means of a photo-etching process. Thereafter, a low-temperature oxide is deposited on the entire surface of the resultant structure by a CVD method and is etched anisotropically, thereby forming spacers 46 on the sidewalls of the first pattern 55. Next, the second material layer is etched along with the third material layer excluding the bottom portion 48a of the first pattern 55.
Referring to FIG. 2, after etching the first conductive layer 50 by performing an anisotropic etching process, using spacer 46 as an etching mask and first material layer 29 as an etching end-point detecting layer (whereby the first pattern is also removed), the remnant of the second material layer is removed by an anisotropic etching process. At this time, the first material layer 29 is overetched, such that voids may be produced after the subsequent process of forming the plate electrode. Then, an impurity-doped polycrystalline silicon layer is deposited on the entire surface of the resultant structure by a CVD method, thereby forming a second conductive layer which is etched anisotropically to thereby form cylindrical electrodes 52a and 52b on both sidewalls of the spacers 46.
Referring to FIG. 3, spacers 46 and first material layer 29 are removed by a wet etching process, thereby forming storage electrodes 200 having a double cylindrical structure. Subsequently, dielectric layer 210 and plate electrode 220 are sequentially formed on the entire surface of the storage electrode 200, thereby completing capacitors C1 and C2.
According to the novel method for manufacturing a capacitor as described above, an internal cylindrical electrode is formed utilizing a real mask pattern for forming the storage electrode, and an outer cylindrical electrode is formed in self-aligned fashion with respect to the internal cylindrical electrode. Therefore, the distance between neighboring capacitors can be reduced to a smaller value than the limitation imposed by photolithographic technology. However, as shown in FIG. 2, if the first material layer is over-etched, voids may be generated after the plate electrodes are formed, which results in degraded reliability of the memory cells.
Based on the above, it can be appreciated that there presently exists a need in the art for a method for manufacturing a capacitor which overcomes the shortcomings of the present inventors' above-described previously proposed method. The present invention fulfills this need.